1. Field of the Invention
This invention generally relates to a digital circuit design assist system and a method thereof. More particularly, the present invention relates to a digital circuit design assist system and a method thereof for designing a desired large-scale digital circuit, using work stations, which can generate functional models consisting of hardware for a desired digital circuit by using a hardware description language such as VHDL, can convert a functional model to a structural model by logic synthesis means, can generate the structural model by direct coding means (text editor) or image processing means (schematic capture), can independently verify the logic of the digital circuit as a whole as one digital circuit when only the functional models exist when the functional models and the structural models exist in a mixed state or when the structural models alone exist, and can further independently verify hardware and software as to whether or not a desired digital circuit can be obtained as a digital circuit comprising a unitary combination of the hardware and the software by loading the software object code of the digital circuit to memory inside the virtual hardware.
2. Description of the Related Art
Because digital circuits at the early stage of their development were limited in size, design and verification of these digital circuits as generally carried out by the steps of designing a logic circuit comprising the combination of components constituting a digital circuit such as resistors, capacitors, ICe, MSIs, LSIs, etc, designing a component arrangement diagram for laying out these components on a printed circuit board and a wiring diagram for wiring connecting the components, actually mounting the selected components on the printed circuit board on the basis of these designs, supplying a current to the resulting printed board, connecting a peripheral circuit or circuits to the printed board, whenever necessary, and verifying whether or not the functions of the printed board satisfied the intended requirements.
As the scale of the LSIs increased in recent years, design of a digital circuit comprising one integrated circuit or at least one integrated circuit and other components has become very complicated, and the design of the digital circuit and the verification of its logic, the design of the actual assembly of the components forming the digital circuit, the verification of software to be loaded to the memory in the digital circuit, and verification of the integrated circuit or the printed board after actual mounting, need an extremely long time.
Recently, design and verification of digital circuits has been carried out using EWSs (Engineering Work Stations). In other words, this system comprises generating functional models constituting a desired digital circuit by coding in a predetermined language, converting all these functional models to structural models by predetermined logic synthesis means, verifying the hardware by the use of a simulator which makes it possible to observe the output waveforms of these structural models on a CRT screen capable of displaying the structural models such as a logic analyzer, producing an actual device on the basis of the structural models only when they pass this verification, such as an LSI itself or a printed board having the LSI and other components mounted thereto, loading a software to a storage unit of the printed board to as to test the actual device, whenever necessary, and thus verifying both the hardware and the software of the desired digital circuit (logic).
As described above, recent design and verification methods for digital circuits cannot verify the digital circuits having software loaded into the hardware thereof unless the actual device is fabricated. If any problem exists, a designer of the hardware and a designer of the software separately examine the hardware design and the software design to determine where the problem exists. If the problem exists in the hardware, the LSI or the printed board is repaired or a new product is produced, and if the problem exists in the software, the program is corrected and the corrected program is again loaded into the hardware so that the hardware and the software of the digital circuit can again be verified in the actual device after the failure of the design is corrected. If another problem remains to be solved, the procedures described above are repeated and verification of the actual device is again effected. However, this system requires excessive time and labor for tentatively producing the hardware. Furthermore, design of the digital circuit and design of the hardware for verification require large numbers of drawings, and a very long time is needed before the design of production hardware is completed.